The present invention relates to a method of fabricating integrated circuits, and specifically, to a method of making a dual damascene structure.
The large integration of semiconductor ICs has been accomplished by a reduction in individual device size. As the integration level of semiconductor devices, increases, each cell generally is reduced in size. To provide for such reduction in cell size, various techniques have been used to improve the performance of the device. For example, DRAM has been increased cell capacitance by increasing the effective area of a cell capacitor. To increase the capacitor""s effective area, stacked-capacitor and trench-capacitor structures, as well as combinations thereof, have been developed. With this reduction of device size, many challenges arise in the manufacture of the ICs. Each device requires interconnections for exchanging electrical signals from one device to another device. Specially, the high performance integrated circuits have multi-level connections. Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements.
Many devices includes conductive lines for performing certain function, such as a bit line contact and a storage node contact must all be formed in a DRAM unit cell. Thus, design rules for minimizing area and ensuring adequate process margin are required. A variety of techniques are employed to create interconnect lines and vias. One such technique involves a process generally referred to as dual damascene, which includes forming a trench and an underlying via hole. The trench and the via hole are simultaneous filled with a conductor material, thereby simultaneously forming an interconnect and an underlying plug. This is a preferred structure for low RC interconnect structures. Interconnect structures containing copper are typically fabricated by a Damascene process.
U.S. Pat. No. 6,140,226 to Grill, et al., entitled xe2x80x9cDual damascene processing for semiconductor chip interconnectsxe2x80x9d. The prior art involves the Dual Damascene process. A further prior art may refer to U.S. Pat. No. 6,133,140 to Yu, et al., entitled xe2x80x9cMethod of manufacturing dual damascene utilizing anisotropic and isotropic propertiesxe2x80x9d. Another one of the arts related to the dual damascene is disclosed in U.S. Pat. No. 6,077,770. However, none of the prior art with the capability to control the width of the conductive line.
What is needed is a method of controlling the wide of the upper conductive line for dual damascene.
The object of the present invention is to form a conductive plug with the capability to control the width of the conductive line for dual damascene.
A method for manufacturing a dual damascene structure comprises forming a first conductive layer over a substrate. An isolation pillar is formed on the first conductive layer. A second conductive layer is next formed along a surface of the isolation pillar and the first conductive layer. A second isolation layer is formed over the second conductive layer. A portion of the second isolation layer is removed, thereby exposing the isolation pillar. A third isolation layer is formed on the first isolation layer. Subsequently, the third isolation layer is to etched to form a trench in the third isolation layer. The isolation pillar is then removed, thereby forming an opening in the first isolation layer. Then, a conductive material is refilled in the trench and the opening, thereby connecting to the first conductive layer.
The dual damascene structure comprises a first conductive layer 6 over a substrate. A conductive plug 20 is formed on the first conductive layer 6. A second conductive layer 10 is formed on the surface of the first conductive layer and on the side wall of the conductive plug 20. A further isolation layer 12 is formed on the second conductive layer 6 and another isolation layer 14 is formed on the isolation layer 12 to have a trench exposing a portion of the isolation layer 12 and the plug 20. A further conductive material 20 is filled into the trench and connect to the conductive plug.